OrCAD PSpice. Анализ электрических цепей - [152]
>.model DINSTM dinput (
>+ s0name = "0" s0t s0rlo=.5 s0rhi=1k
>+ s1name="1" s1tsw=0.5ns s1rlo=1k s1rhi=.5
>+ s2name="X" s2tsw=0.5ns s2rlo=0.429 s2rhi=1.16; 313ohm, 1.35v
>+ s3name="R" s3tsw=0.5ns s3rlo=0.429 s3rhi=1.16; 313ohm, 1.35v
>+ s4name="F" s4tsw=0.5ns s4rlo=0.429 s4rhi=1.16; 313ohm, 1.35v
>+ s5name="Z" s5tsw=0.5ns s5rlo=1MEG s5rhi = 1MEG
>+ )
>.model DINSTM ОС dinput (
>+ s0name="0" s0tsw=0.5ns s0rlo=.5 s0rhi=1k
>+ s1name="1" s1tsw=0.5ns s1rlo=1MEG s1rhi=1MEG
>+ s2name="X" s2tsw=0.5ns s2rlo=0.429 s2rhi = 1.16; .313ohm, 1.35v
>+ s3name="R" s3tsw=0.5ns s3rlo=0.429 s3rhi=1.16; .313ohm, 1.35v
>+ s4name="F" s4tsw=0.5ns s4rlo=0.429 s4rhi=1.16; .313ohm, 1.35v
>+ s5name="Z" s5tsw=0.5ns s5rlo=1MEG s5rhi=1MEG
>+ )
Модели по умолчанию и модели подсхем I/O по умолчанию
>.model IO_DFT uio (
>+ drvh = 50 drvl = 50
>+ AtoD1 = "AtoD_STD" AtoD2 ="AtoD_STD_Nx"
>+ AtoD3 = "AtoD_STD" AtoD4="AtoD_STD_fX"
>+ DtoA1 = "DtoA_STD" DtoA2="DtoA_STD"
>+ DtoA3 = "DtoA_STD" DtoA4="DtoA_STD"
>+ DIGPOWER="DIGIFPWR"
>.model IO_DFT_OC uio (
>+ drvh=1MEG drvl=50
>+ AtoD1="AtoD_STD" AtoD2="AtoD_STD
>+ AtoD3="AtoD_STD" AtoD4="AtoD_STD"
>+ DtoA1 ="DtoA_STD_ОС" DtoA2 = "DtoA_STD_OC"
>+ DtoA3 ="DtoA_STD_ОС"
>+ DtoA4 = "DtoA_STD_OC"
>+ DIGPOWER="DIGIFPWR"
>+ )
Форма для подсхемы AtoD по умолчанию
>. subckt AtoDDEFAULT A D DPWR DGND
>+ params: CAPACITANCE=0
>A DGND D074 DGTLNET=D IO_DFT
>. ends
Форма для подсхемы DtoA по умолчанию
>.subckt DtoADEFAULT D A DPWR DGND params: DRVL=0 DRVH=0 CAPACITANCE=0
>N1 A DGND DPWR DIN74 DGTLNET=D IO_DFT
>C1 A DGHD {CAPACITANCE=0.1pF}
>.ends
Семейство 74/54 (стандартные микросхемы TTL) 7400 модели I/O
>.model 10 STD uio (
>+ drvh= 96.4 drvl = 104
>+ AtoD1 ="AtoD_STD" AtoD2="AtoD_STD_NX"
>+ AtoD3="AtoD_STD" AtoD4="AtoD_STD_NX"
>+ DtoA1="DtoA_STD" DtoA2 ="DtoA_STD"
>+ DtoA3="DtoA_STD" DtoA4="DtoA_STD"
>+ tswhl1=1.373ns tswlh1=3.382ns
>+ tswhl2=1.346ns tswlh2=3.424ns
>+ tswhl3=1.511ns tswlh3=3.517ns
>+ tswhl4=1.487ns tswlh4=3.564ns
>+ DIGPOWER="DIGIFPWR"
>+ )
>.model IO_STD_ST uio (
>+ drvh=96.4 drvl=104
>+ AtoD1="AtoD_STD_ST" AtoD2="AtoD_STD_ST"
>+ AtoD3="AtoD_STD_ST" AtoD4="AtoD_STD_ST"
>+ DtoA1="DtoA_STD" DtoA2 ="DtoA_STD"
>+ DtoA3="DtoA_STD" DtoA4="DtoA_STD"
>+ tswhl1=1.373ns tswlh1=3.382ns
>+ tswhl2=1.346ns tswlh2=3.424ns
>+ tswhl3=1.511ns tswlh3=3.517ns
>+ tswhl4=1.487ns tswlh4=3.564ns
>+ DIGPOWER="DIGIFPWR"
>+ )
>.model 10 STD ОС uio (
>+ drvh = 1MEG drv1 = 104
>+ AtoD1="AtoD_STD" AtoD2="AtoD_STD_NX"
>+ AtoD3="AtoD_STD" AtoD4="AtoD_STD_NX"
>+ DtoA1="DtoA_STD_OC" DtoA2="DtoA_STD_OC"
>+ DtoA3="DtoA_STD_OC" DtoA4="DtoA_STD_OC"
>;tsw values measured with 33 0 ohm pull up
>+ tswhl1=2.617ns tswlh1=1.432ns
>+ tswhl2=2.598ns tswlh2=1.460ns
>+ tswhl3=2.747ns tswlh3=1.589ns
>+ tswhl4=2.732ns tswlh4=1.615ns
>+ DIGPOWER="DIGIFPWR"
>+ )
7400 стандартная подсхема AtoD
>.subckt AtoD STD A D DPWR DGND params; CAPACITANCES
>CO A DGND D074 DGTLHET IO_STD
>C1 A DGND {CAPACITANCE=0.1pF}
>DO DGND a D74CLMP
>D 1 2 D74
>D2 2 DGND D74
>R1 DPWR 3 4k
>Q1 1 3 A 0 Q74 ; substrate should be DGND
>.ends
>.subckt AtoD_STD_NX A D DPWR DGND params: CAPACITANCE = 0
>CO A DGND D074_NX DGTLNET = D IO_STD
>C1 A DGND {CAPACITANCE+0.1pF}
>D0 DGND a D74CLMP
>D1 1 2 D74
>D2 2 DGND D74
>R1 DPWR 3 4k
>Q1 1 3 A 0 Q74 ; substrate should be DGNC
>.ends
7400 стандартная подсхема DtoA
>.subckt DtoA_STD D A DPWR DGND
>+ params: DRVL=0 DRVH=0 CAPACITANCE=0
>M1 A DGND DPWR DIH74 DGTLNET=DIO_STD
>C1 A DGND {CAPACITANCE=0.1pF}
>.ends
7400 подсхема DtoA с открытым коллектором
>.subckt DtoA_STD_OC D A DPWR DGND
>+ params: DRVL=0 DRVH=0 CAPACITANCE=0
>N1 A DGND DPWR DIN74_ОС DGTLNET=D IO_STD_OC
>C1 A DGND {CAPACITANCE=0.1pF}
>.ends
7400 Модели цифровых входов/выходов (I/O)
>.model DIN74 dinput (
>+ s0name="0" s0tsw=3.5ns s0rlo=7.13 s0rhi = 389 ; 7ohm, 0.09v
>+ s1name ="1" s1tsw=5.5ns s1rlo = 467 s1rhi = 200; 140ohm, 3.5v
>+ s2name="X" s2tsw=3.5ns s2rlo=42.9 s2rhi = 116 ;31.3011m, 1.35v
>+ s3name="R" s3tsw=3.5ns s3rlo=42.9 s3rhi = 116 ; 31.3ohm, 1.35v
>+ s4name="F" s4tsw=3.5ns s4rlo=42.9 s4rhi=116 ; 31.3ohm, 1.35v
>+ s5name="Z" s5tsw=3.5ns s5rlo=200K s5rhi=200K
>+ )
>.model DIN74_OC dinput (
>+s0name="0" s0tsw=3.5ns s0rlo=7.13 s0rhi=389 ; 7ohm, 0.09v
>+ s1name="l" s1tsw=5.5ns s1rlo=200K s1rhi=200K
>+ s2name="X" s2tsw=3.5ns s2rlo=42.9 s2rhi = 116 ;31.3ohm, 1.35v
>+ s3name="R" s3tsw = 3.5ns s3rlo = 42.9 s3rhi = 116; 31.3011m, 1,35v
>+ s4name="F" s4tsw = 3.5ns s4rlo = 42.9 s4rhi = 116 ; 31.3ohm, 1.35v
>+ s5name="Z" s5tsw=5.5ns s5rlo=200K s5rhi=200K
>+ )
>.model D074 doutput (
>+ s0narae="X" s0vlo = 0 .8 s0vhi=2.0
>+ s1name="0" s1vlo = -1.5 s1vhi = 0.8
>+ s2name="R" s2vlo=0.8 s2vhi = 1.4
>+ s3name="R" s3vlo=1.3 s3vhi=2.0
>+ s4name="X" s4vlo=0.8 s4vhi=2.0
>+ s5name="1" s5vlo=2.0 s5vhi=7.0
>+ s6name="F" s6vlo=1.3 s6vhi=2.0
>+ s7name="F" s7vlo=0.8 s7vhi=1.4
>+ )
>.model D074_NX doutput (
>+ s0name = "0" s0vlo=-1.5 s0vhi = 1.35
>+ s2name = "1" s2vlo=1.35 s2vhi = 7.0
>+ )
>.model D074_ST doutput (
>+ s0name="0" s0vlo=-1.5 s0vhi = 1.7
>+ s1name="1" s1vlo=0.9 vhi = 7.0
>+ )
Модели компонентов ТТЛ
Эти значения параметров взяты из книги Hodges, David A., and Horace G. Jackson, 1983, Analysis and Design of Digital Integrated Circuits, New York: McGraw-Hill, p. 301.
>model D74 d (
>+ is = 1e-16 rs = 25 cjo = 2pf